Non-volatile memory devices such as EEPROMs or flash EEPROMs comprise memory cells including a floating gate which stores data and a control gate which applies voltage to the floating gate. The memory cells are formed on a semiconductor substrate including source/drain regions.
FIGS. 1a and 1b are cross-sectional views of a prior art flash memory cell during fabrication.
Referring to FIG. 1a, an N-well 12 and a P-well 13 are formed in a silicon substrate 11. The N-well 12 and/or the P-well 13 may be formed, for example, by ion implantation. A source/drain region 14 is defined in the P-well 13 by, for example, ion implantation. A gate oxide 15, a floating gate 17, an oxide-nitride-oxide (ONO) layer 18, and a control gate 19 are then formed by ion implantation, photoresist coating, patterning, development, deposition, etc. The floating gate 17 stores electric charges and the control gate 19 is used to apply voltage to the floating gate 17. The floating gate 17 and the control gate 19 are formed into a tandem structure. Spacers 20 of SiN are formed to isolate and protect the gate area including the floating gate 17 and the control gate 19. A source/drain region 14 is defined in the upper part of the P-well 13, and positioned between adjacent gate spacers 20 of adjacent gate areas. A unit block of a transistor consists of the floating gate 17, the control gate 19, and the source/drain region 14. In addition, silicide 16 and a borderless contact (BLC) layer 21 are formed to connect the flash memory cell to an external terminal such as a word line or a bit line.
Referring to FIG. 1b, after the formation of the spacers 20, borophosphorsilicate glass (BPSG) 22 is deposited over the substrate. Generally, in order to ensure the characteristics of the logic transistors and to reduce the costs in fabricating an embedded flash memory, a SiN layer is deposited and etched to form the spacers 20. The BPSG layer 22 is then deposited over the gate structure to form a passivation layer of the flash memory cell.
However, because the gap between the SiN spacers is very narrow in a cell array, if the BPSG layer 22 is deposited after formation of the spacers 20, voids 23 are formed in the gap between the SiN spacers 20. The voids 23 may change the characteristics of each cell. In addition, the size of the voids 23 vary according to a critical dimension of polysilicon constituting each cell. This variation in the sizes of the voids may also change characteristics of the cells. For example, the voids function as parasitic capacitances which decrease the operating speed of the flash memory device and function as points of stress and leakage during device operation, thereby causing deterioration of device reliability and characteristics.
To obviate the problems due to voids formed in the passivation layer in fabricating a non-volatile memory device, Mei et al., U.S. Pat. No. 6,475,895, describes a semiconductor device having a passivation layer and a method for its fabrication. This U.S. patent provides a final passivation layer, especially for flash memory and other non-volatile memory technologies, that can overcome problems due to a narrow gap between metal lines which cannot be completely filled by using the conventional film deposition techniques of chemical vapor deposition (CVD) or plasma enhanced chemical vapor deposition (PECVD). A semiconductor device structure described in the above-mentioned U.S. patent includes a first layer of high density plasma (HDP) oxide and an overlying layer of silicon oxynitride. Application of the HDP oxide to a pattern of metal structures fills gaps between the metal structures and allows for the void free deposition of the silicon oxynitride layer. The silicon oxynitride layer provides a hard outer coating to the passivation coating.